1. Field of the Invention
The present invention relates to a method for providing time synchronization in a distributed control system.
2. Description of the Related Art
In general, a distributed control system includes a set of nodes interconnected through one or multiple network communication links. The network communication links may include a packetized link, such as an Ethernet, or one or more of various packetized links, which can be employed in a distributed control system application. In the distributed control systems, there is a recently growing awareness of the need to support time sensitive traffic. Hence, it is necessary to synchronize a clock between nodes of a distributed control system.
In a distributed control system including a plurality of clocks, time synchronization must be employed in order to reduce instabilities inherent in source oscillators and time drift effect in use environment conditions (refers to reference 1 below). Especially, a residential bridge, referred as a residential Ethernet, is considering time synchronization in order to provide traffic streaming, sampling of data streams in source and destination devices, and synchronized clocks for indication of such streams (refers to reference 2 below). In order to perform a precise time synchronization, the distributed control system must have synchronization performance in which a slave clock can be locked to a master clock in both clock time and a clock frequency.
Referring to reference [3] below, an IEEE 1588 standard prescribes time formats and defines a plurality of messages that can be used to distribute timing information, but does not define a scheme for achieving time synchronization. Reference [1] discloses a frequency compensation clock that can perform precise frequency and time synchronizations using an IEEE 1588 protocol, in order to change timing information.
FIG. 1 is a ladder diagram illustrating a basic operation procedure for time synchronization in a general distributed control system, which discloses a basic operation between a master clock and a slave clock in a distributed control system according to the IEEE 1588 protocol. Referring to FIG. 1, the master clock periodically transmits a synchronization message (sync) including its own lunching time to the slave clock, thereby performing an operation for time synchronization at regular intervals. The master clock can transmit opening time through an optional message (follow-up) in a similar manner. A delay request (not shown) is transmitted from the slave clock to the master clock in order to confirm the transmission delay, and a delay response (not shown) is transmitted from the master clock to the slave clock in response to the delay request, so that information for confirming the transmission delay time can be obtained.
Through detection of arrival time of such a sync, reception of launching time within the sync, and subtraction of transmission delay time from the master clock to the slave clock, the slave clock recognizes its own time offset related to the master clock, and thus compensates for its own operation frequency and time values. Reference [3] discloses a detailed procedure for the IEEE 1588 protocol.
FIG. 2 is a block diagram illustrating a main part of a frequency compensation clock in a general distributed control system, which has the same construction as disclosed in the reference [1]. Referring to FIG. 2, the frequency compensation clock includes a frequency compensation module 210 and a clock counter 220. As indicated in more detail by the dotted lines of FIG. 2, the frequency compensation module 210 may include a frequency multiplier 214 and a frequency compensation value register 212. Before a local oscillator frequency is provided to the clock counter 220, it is multiplied to a frequency compensation value in the frequency compensation module 210, and thus the frequency is corrected. As disclosed in reference [1], clocks with this construction can compensate for both a time offset and a frequency by properly updating a frequency.
In the slave clock, an initial value of the frequency compensation value may be scheme-dependent. In a clock setup environment of FIG. 2, a frequency compensation value may be set to 1, differently from reference [1], but which neither has an effect on an operation process nor leads to another result.
Hereinafter, the frequency update scheme will be described in more detail with reference to FIG. 1 and is performed as follows. As illustrated in FIG. 1, at MasterSyncTimen, the master transmits a sync to the slave. Herein, the corresponding sync includes the time value MasterSyncTimen by the time-stamping. Herein, the ‘n’ corresponds to a count value of the sync. The slave receives the sync when its own local clock is SlaveClockTimen. Herein, the slave computes master clock time MasterClockTimen as expressed by an equation below.MasterClockTimen=MasterSyncTimen+MasterToSlaveDelay
In the equation above, the MaterToSlaveDelay corresponds to a transmission delay time value.
A master clock count MasterClockCountn of a current synchronization cycle is determined as expressed by an equation below.MasterClockCountn=MasterClockTimen−MasterClockTimen−1 
A slave clock count SlaveClockCountn for the current synchronization cycle is determined as expressed by an equation below.SlaveClockCountn=SlaveClockTimen−SlaveClockTimen−1 
Difference between the master and slave clock counts for the current synchronization cycle, ClockDiffCountn is determined as expressed by an equation below.ClockDiffCountn=MasterClockTimen−SlaveClockTimen 
The frequency scaling factor of the slave clock, FreqScaleFactorn is determined as expressed by an equation below.FreqScaleFactorn=(MasterClockCountn+ClockDiffCountn)/SlaveClockCountn 
Then, the frequency compensation value of the current slave clock, FreqCompVlauen is computed as expressed by equation 1 below.FreqCompValuen=FreqScaleFactorn*FreqCompValuen−1  (1)
The theoretical result of performing an operation according to the same manner is that at SlaveClockTimen+1, the frequencies of master and slave clocks would lock, and the difference ClockDiffCountn+1 between the two clocks would be zero.
The manner as described above is used in current frequency compensation clocks compensating for both the frequency and the time offset. Herein, the process for computing the frequency scaling factor is a key point in the manner.
Meanwhile, in the manner for computing the frequency scaling factor as expressed in equation 1, it can be understood that periodical frequency and time offset are periodically and simultaneously compensated using the sync in each reception cycle of the sync. However, if multiple communication networks are hierarchically connected through bridges (switches) by using such a manner as disclosed in reference [4] below, the number of bridges passed by along synchronization paths from a grand master to each slave increases. Therefore, synchronization errors are accumulated when the bridges are passed by through and may exponentially increase.